This application claims the priority benefit of Taiwan application serial no. 91107692, filed Apr. 16, 2002.
1. Field of Invention
The present invention relates to a method for fabricating a non-volatile memory. More particularly, the present invention relates to a method for fabricating a non-volatile memory having a P-type floating gate.
2. Description of Related Art
A non-volatile memory is capable of retaining data even when the power is switched off. The non-volatile memory devices can be divided into several types according to their operating methods, including mask read-only memory (Mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (E2PROM), and Flash memory.
Among various types of non-volatile memory, EPROM, E2PROM and Flash memory all use floating gates for charge storage, wherein the floating gates usually comprise N-doped polysilicon. A conventional non-volatile memory having polysilicon floating gates and the fabrication thereof are described as follows.
Refer to FIGS. 1Axcx9c1C, which illustrate the process flow of fabricating a conventional non-volatile memory having an N-type floating gate in a cross-sectional view.
Refer to FIG. 1A, a tunnel oxide layer 102 is formed on a substrate 100 and then a polysilicon floating gate 104 is formed on the tunnel oxide layer 102.
Refer to FIG. 1B, an N-type buried drain 106 is formed in the substrate 100 beside the floating gate 104 by conducting an N-type ion implantation with the floating gate 104 as a mask. Since the floating gate 104 is simultaneously doped with the N-type ion used for implantation, the floating gate 104 has N-type conductivity.
Refer to FIG. 1C, a conformal dielectric layer 108 is formed on the tunnel oxide layer 102 and the floating gate 104 to serve as an inter-gate dielectric layer. A control gate 110 is then formed on the conformal dielectric layer 108.
The non-volatile memory having a floating gate is programmed by injecting electrons into the floating gate. However, since the floating gate in the conventional non-volatile memory is of N-type, the excess electrons at the interface between the floating gate and the tunnel oxide layer easily escape from the floating gate and tunnel into the substrate though the tunnel oxide layer. A leakage current is thus caused and the data retaining ability of the floating gate is therefore restricted.
Accordingly, this invention provides a method for fabricating a non-volatile memory having a P-type floating gate to solve the leakage problem encountered in the case of the N-type floating gate.
This invention also provides a method for fabricating a non-volatile memory having a P-type floating gate to improve the data retaining ability of the non-volatile memory.
The method for fabricating a non-volatile memory having a P-type floating gate of this invention is described as follows. A tunnel oxide layer is formed on a substrate and then a first patterned polysilicon layer, which comprises undoped polysilicon, is formed on the tunnel oxide layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating layer is formed covering the tunnel oxide layer and the first polysilicon layer. A chemical mechanical polishing (CMP) process or an etching-back process is performed to remove a portion of the insulating layer until the first polysilicon layer is exposed, whereby an insulating structure is left on the tunnel oxide layer on the buried drain. Thereafter, a second patterned polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion implantation is performed to dope the second polysilicon layer and then a dielectric layer is formed on the second polysilicon layer and the insulating structure. A control gate, which may also be of P-type, is formed on the dielectric layer. The P-type ions in the second polysilicon layer will diffuse into the first polysilicon layer during subsequent thermal processes to make the whole floating gate have P-type conductivity.
Since this invention uses a P-type floating gate in the non-volatile memory, the electrons stored in the floating gate will recombine with electron holes and the possibility of electrons escaping from the floating gate is therefore reduced, which means that the leakage current is decreased. Consequently, the data retaining ability of the non-volatile memory can be enhanced.
Moreover, since the P-type ion is implanted only into the second polysilicon layer but not into the first polysilicon layer, the P-type ion can be prevented from diffusing into the substrate through the tunneling layer during subsequent thermal processes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.